In this module, let us discuss the following flip-flops using second method. In second module, you can directly implement the flip-flop, which is edge sensitive. So that the combination of these two latches become a flip-flop. In first method, cascade two latches in such a way that the first latch is enabled for every positive clock pulse and second latch is enabled for every negative clock pulse. You can implement flip-flops in two methods. Those are the basic building blocks of flip-flops. You covered about latches in the previous modules. Master-slave JK flip-flop constructed by using NAND gates.Differences between latches and flip-flops.Verilog Test bench for synchronous D Flip-Flop.įigure 6.This site uses Just the Docs, a documentation theme for Jekyll. // Wait 100 ns for global reset to finishįigure 5.// Instantiate the Unit Under Test (UUT).Verilog Test Bench for synchronous D Flop-Flop (DFF_tb.v) Verilog Code for synchronous D Flop-Flop (DFF.v)įigure 4.Verilog module of synchronous D Flip-Flop

The output line Q takes the same value as that in the input line D on the rising edge of the clock line Clk when the reset line is at low.įigure 3. The output lines are Q and Qbar (complement of output line Q). The control lines to the module include a 1-bit clock line Clk which is supplied by the 50 MHz on-board clock generator and a 1-bit active high reset. The input to the module is a 1-bit input data line D. Truth table of synchronous D Flip-Flopįigure 3 shows the Verilog module of D Flip-Flop. The inputs to the D Flip-Flop are data-bit D, and control lines reset and clock. Block diagram of synchronous D Flip-Flopįigure 2 shows the truth table of synchronous D Flip-Flop which is clocked to the rising edge of input clock. The block diagram of synchronous D Flip-Flop is shown in Figure 1.įigure 1. Synchronous D Flip-Flop, thus, has output which is synchronized with the either the rising edge or the falling edge of the input clock pulse. If the output is clocked then the D Flip-Flop is synchronous D Flip-Flop. The output of the Flip-Flop may be clocked. A D Flip-Flop can be made from a Set/Reset Flip-Flop by tying the set line to the reset line through an inverter. It can be thought of as a basic memory cell. this Flip-Flop stores the value on the data line. The D in D Flip-Flop stands for Data i.e. The output of a D Flip-Flop tracks the input, making transitions which match those of the input.

D flip flop